CPU Microcode & Core Design
Owning CPU-core microcode features end to end - from specification and patch integration to conformance triage and production handoff.
System Design Engineer
Engineering performance & security into modern processors.
System design engineer specializing in high-performance CPU cores, hardware security, and large-scale validation - bridging industry engineering with academic research.
10+ Years across silicon, validation & research
IEEE Senior Member (2025)
30+ Students mentored & Industry Advisory Council member
50+ Peer-reviewed manuscripts evaluated for IEEE
$300K National Science Foundation research funding
Overview
Everything in one place
A complete view of my work - jump straight to what interests you.
01 About Background, education & skills 02 Experience Roles across silicon & validation 03 Research Low-power hardware security 04 Publications Peer-reviewed papers & talks 05 Projects Automation, silicon & ML work 06 Achievements Awards, honors & memberships 07 Featured Media, interviews & recognition 08 Mentoring & Service Peer review & advising
Security
Hardware security, from mitigation to release
Leading validation and release for publicly disclosed processor security advisories and confidential-computing mitigations.
See the work
Research
Research in secure, low-power hardware
My research centers on making security practical for the smallest, most constrained devices. Supported by national research funding (a grant of approximately $300K), I developed chaos-based encryption architectures for low-power IoT and wearable systems - taking ideas from mathematical models all the way to FPGA and CMOS silicon demonstrators.
Explore the research What I do
Areas of focus
Hardware Security
Leading validation and release for publicly disclosed processor security advisories and confidential-computing mitigations.
Validation Automation
Designing automation frameworks and analytics that cut manual effort dramatically and save substantial engineering cost.
Research in Secure Hardware
Nationally funded research on low-power, chaos-based encryption for IoT - from algorithmic modeling to silicon.
Now
Full experience Current role
Advanced Micro Devices (AMD)
Dec 2022 - PresentSenior System Design Engineer · Silicon Core Design & Debug
Driving next-generation server and client CPU-core development, with ownership of microcode, security validation, and large-scale automation.
Selected work
All projects Featured projects
Microcode Integration & Validation Automation Platform
Substantially reduced manual validation effort
Zero-Downtime Microcode Patch-Data Deployment
Reduced remediation cycles from weeks to minutes
Validation Analytics & Traceability Dashboard
Reduced manual planning effort
Research
All publications Recent publications
- 2025
Digital IC Design of a 45nm CMOS Chua Encryption Architecture for Resource-Limited Devices
IEEE ISVLSI 2025
- 2024
Digital IC Design of a 45nm CMOS Chua Encryption Architecture (Poster)
WISE 2024 - Workshop for Women in Hardware & Systems Security
- 2023
Attacks on Continuous Chaos Communication and Remedies for Resource-Limited Devices
ISQED 2023 - International Symposium on Quality Electronic Design
Free mentorship
Book an appointment Let's talk silicon, security & careers
I offer free mentorship sessions for students and early-career engineers exploring processor architecture, hardware security, validation, and research.