Security for the Smallest Devices

Most cryptography assumes you have resources to spare: compute, memory, and power. But the fastest-growing class of connected devices - wearables, implantables, and tiny IoT sensors - has almost none of those. Securing them requires rethinking the problem from the silicon up.

The constraint is the design

On a device measured in microwatts and fractions of a square millimeter, a heavyweight cryptographic block is a non-starter. The challenge is to deliver meaningful security within a power and area budget that leaves room for the device’s actual job - sensing, communicating, and lasting on a small battery.

Why chaos?

Chaotic systems - think of circuits modeled on equations like Chua’s - are extraordinarily sensitive to initial conditions. That sensitivity can be harnessed to scramble a signal in a way that’s cheap to implement in analog or mixed-signal hardware. Implemented carefully, a chaos-based encryption primitive can run at very low frequency and voltage while occupying a tiny footprint.

From equation to silicon

The interesting engineering happens in the translation: modeling the system, generating synthesizable hardware, and validating it both on FPGA and in a CMOS process. Each step forces trade-offs between robustness, power, and area. Getting a working demonstrator down to microwatt-scale power and a sub-0.01 mm-squared footprint shows that on-chip security for constrained devices is not just theoretical.

Where it goes next

The broader goal is on-chip security that integrates directly with sensors, so protection travels with the data from the moment it’s captured. As billions more constrained devices come online, lightweight, hardware-native security stops being a niche research topic and becomes a practical necessity.