A decade across silicon, validation & research

Senior System Design Engineer · Silicon Core Design & Debug

Folsom, CA

Driving next-generation server and client CPU-core development, with ownership of microcode, security validation, and large-scale automation.

• Contribute to an in-house automation platform that streamlines integration of microcode and firmware images for CPU-core patches, working across firmware and platform teams.
• Designed a microcode deployment approach that enables field-issue remediation without firmware re-spins, with verification and sign-off checkpoints built into the standard release process.
• Built analytics and traceability tooling that helps synthesize validation focus areas, improving planning efficiency and leadership visibility into coverage.
• Contributed to validation and release coordination for publicly disclosed CPU security advisories, helping align readiness across industry partners.
• Built an internal CPU-virtualization execution harness that helped isolate pre-tape-out silicon issues and supported rapid fix-and-retest cycles.
• Contributed to a shift-left security release process that improves early defect interception and sign-off quality.
• Perform deep core debug using disassembly traces, cache-footprint analysis, and low-level hardware debug tooling to root-cause functional, performance, and stability anomalies.

Graduate Research Assistant · Electrical Engineering Department

Long Beach, CA

Nationally funded research on CMOS-based, chaos-driven encryption for on-chip integration with low-power sensors.

• Conducted proof-of-concept research on CMOS-based security encryption for on-chip integration with sensors, supported by national research funding.
• Explored optimization techniques for delay reduction and alternative chaotic oscillator systems to support higher-frequency data with further power and area savings.
• Implemented multiple chaotic circuits (Chua's, Lorenz, SprottD, and others) in LTspice and MATLAB to extract power, sensitivity, and design-load characteristics.
• Targeted designs onto an FPGA via a model-based hardware toolchain for hardware co-simulation and resource (LUT) utilization measurement.
• Prepared low-power circuit designs for foundry fabrication and manufacturing-test validation.

Software Engineer · Data Center Group

Bangalore, IN

Led volume validation and power/performance work for AI inference accelerators and server platforms at scale.

• Led volume validation at scale for an AI inference product, mimicking customer data-center environments with open-standard server racks and collaborating cross-geo with customer engineers to surface critical issues before release.
• Contributed to the power-on team for an AI inference accelerator, executing a critical role in power-on exit.
• Owned stress and stability execution for AI workloads across volume nodes and discovered critical stability issues.
• Helped design a custom tool providing single-server access to hundreds of nodes through a centralized management system, enabling full automation for volume validation across 300+ nodes.
• As power & performance validation lead for server platforms, ran full-life-cycle measurements to meet customer performance-per-watt targets using standard memory, integer, and floating-point workloads.
• As automation engineer, designed a centralized, remote power-and-performance validation ecosystem that improved cross-geo co-validation and reduced per-project cost.

Graduate Intern · Data Center Group

Bangalore, IN

Server software integration and validation automation, including custom low-cost test hardware.

• Joined the server software integration team validating internal component integration and evaluating regressions before customer release.
• Contributed to an automation framework for multi-domain automation, reducing software release time to customers.
• Designed a custom low-cost test fixture using a single-board computer and relay switches to replace expensive automation setups.
• Performed hands-on power and performance architecture work on an advanced driver-assistance (ADAS) platform.