Chaos-Based Hardware Cryptography
Designing encryption primitives from chaotic systems (Chua's, Lorenz, SprottD) that provide secure communication with extremely low power and area - suitable for implantable and wearable devices.
Research
Securing the smallest devices
Nationally funded research bringing practical, low-power security to constrained IoT and wearable hardware.
My research centers on making security practical for the smallest, most constrained devices. Supported by national research funding (a grant of approximately $300K), I developed chaos-based encryption architectures for low-power IoT and wearable systems - taking ideas from mathematical models all the way to FPGA and CMOS silicon demonstrators.
Focus
Research areas
Low-Power CMOS & FPGA Implementation
Translating algorithmic models into synthesized RTL and physical design at 45nm, and validating on FPGA - achieving microwatt-scale power and sub-0.01 mm^2 footprints.
Secure Communication for Constrained Devices
Analyzing attacks on continuous chaotic communication and developing remedies, including memristor-based transceivers resilient to eavesdroppers and untrusted foundries.
Funding
Nationally funded research
Selected as a graduate research assistant on a project advancing efficient, reliable, and secure chaotic communication for wearable devices - supported by a national research grant of approximately $300,000.
Output
View all Publications & talks
My research has produced peer-reviewed journal and conference papers, a master's thesis, and conference presentations. The full list - including industry technical papers - lives on the Publications page, and the complete record with citations is on Google Scholar.